Generally, switching regulators are employed as DC power sources. In some applications, when the regulator is first turned on, a pre-existing voltage exists at the switching regulator output terminal, e.g., a pre-charge voltage. This pre-charge voltage may either result from an external voltage source, or a residual charge that exists across the load, for example, a residual voltage across output filter capacitors of the switching regulator. Many switching regulators employ output switches that alternately connect a switched node to an input voltage and ground when the switching regulator is on. Often, these output switches are solid state devices (e.g., MOSFETs) that allow current to flow through the switch in either direction from a switch drain terminal to a switch source terminal. Thus, under some operating conditions, operation of the output switches may allow a reverse current to flow from the regulator output terminal to ground through a regulator output filter inductor, e.g. the switch acts as a current sink. This condition is especially problematic for switching regulators that employ a soft start, i.e, gradually increase a target regulator output voltage at startup. When switching regulators that employ a soft start are first turned on (i.e., the switching controller first begins to supply a switching controller output to turn on one of the output switches), they detect that the output voltage at the regulator output terminal is greater than the target regulator output voltage and allow a reverse current that may drain all or part of the pre-charge voltage present at the regulator output terminal.
FIG. 1 is a prior art circuit employing a zero-crossing detector to prevent the pre-charge voltage from being drained when the switching regulator is turned on. The switching regulator 9 includes a switching controller 10, a first switch 11, a second switch 12, an output filter 14, and a zero-crossing detector 16. The first and second switches 11, 12 operate in response to a logic signal appearing at a switching controller output 22. First switch 11 connects a switched node 30 to an input voltage terminal 24 when it is on. When the second switch 12 is on, it connects the switched node 30 to ground. A first terminal 28 of the zero-crossing detector is connected to the switched node 30. The switched node 30 is also connected to an output filter inductor 34 terminal 36. A second terminal 33 of zero-crossing detector 16 is connected to ground. The output terminal 30 of the zero-crossing detector 16 is connected to a first input 38 of an AND gate 40 that supplies a logic signal to a gate of the second switch 12. A second input 42 of AND gate 40 is the inverted output signal of switching controller 10. The circuit is configured such that the first switch 11 conducts when the output of switching controller 10 is a high logic state. Provided that a reverse current flow is not detected, the second switch 12 conducts when the output of the switching controller is a low logic state.
The zero-crossing detector produces a low logic state at the zero-crossing detector output terminal 36 to indicate a reverse current flow when the voltage on switched node 30 is positive with respect to ground. The low logic state is supplied to first input 38 of AND gate 40. In this condition, a low logic signal is maintained at the AND gate output terminal 44, regardless of the logic value present at the second AND gate input 42. As a result, second switch 12 is prevented from being turned on. Although this approach detects the reverse current flow through switch 12, it requires a fast zero-crossing detector to prevent the pre-charge voltage from being drained.
Further, the zero-crossing detector of FIG. 1 operates in an environment where the signal to noise ratio is very low. In this environment, the signal that is being measured across second switch 12 (i.e., between a first inductor terminal 46 and a ground) may be as low as 5 mV. However, the noise signal at switched node 30 may be as high as several volts. Consequently, it is difficult to accurately detect reverse current. Additionally, the circuit of FIG. 1 may complicate an integrated circuit comprising switching regulator 9 because the circuit requires an additional pin to provide access to switched node 30.
The present invention addresses these shortcomings.